The present invention relates in general to voltage translators, and more particularly, to an Emitter Coupled Logic (ECL) to Complimentary Metal Oxide Semiconductor (CMOS) voltage translator combining high speed operation and reduced power consumption.
It is well known that many of today's complex systems mix and match integrated circuits (ICs) of different logic families to accomplish a series of interrelated functions. In one example, signals produced in one logic family, ECL, are translated to levels compatible with another logic family, CMOS, for further processing. One known voltage translator, disclosed in U.S. Pat. No. 4,644,194, comprises an emitter-follower NPN transistor having its emitter coupled to the base of a second transistor through a first resistor. The collector-emitter conduction path of the second transistor is coupled between an upper power supply conductor operating at V.sub.CC and a lower power supply conductor operating at V.sub.EE through a pair of serially coupled diodes and a second resistor for translating the ECL input signal, which is typically referenced to the upper V.sub.CC rail, to a potential across the second resistor referenced to the lower V.sub.EE rail. The base of a third transistor is responsive to the potential developed across the second resistor for providing the output signal at the collector thereof. In addition, a regulation circuit is coupled to the base of the second transistor to compensate for changes in V.sub.EE such that the output signal is independent of power supply variation.
When a logic high ECL input signal is applied at the base of the emitter-follower transistor, collector current flows through the first resistor and turns on the second transistor to establish a current flowing through its collector-emitter conduction path. The impedance between the emitter of the second transistor and power supply conductor V.sub.EE is made very low (three PN junctions) for providing high speed operation, but the low impedance also permits excessive current to flow through the translating conduction path. The large current tends to saturate the third transistor and generate excessive power dissipation, both of which are undesirable.
Hence, there is a need for an improved ECL to CMOS translator for combining the features of high speed operation and reduced power consumption with minimal additional components.